This invention relates to a data processing system of the multi-processor type, having a plurality of central processing units.
In a data processing system of the multi-processor type configuration with its plural central processing units interconnected functionally with one another, all the central processing units share a main memory in the system with one another. Each central processing unit is furnished with a high-speed buffer memory having a smaller capacity. The buffer memories are allowed to take in and store therein parts of the data stored in the main memory. By using the data transferred to the buffer memories, the access time for data can be shortened since if one of the central processing units needs a piece of data stored in both the main memory and the associated buffer memory, it can obtain the desired data by making an access to the high-speed buffer memory, not directly to the main memory. If a central processing unit finds that a desired piece of data is not present in the associated buffer memory, it makes an access to the main memory to obtain the necessary data and also to transfer the same data into the associated buffer memory.
The buffer memories are thus dedicated to the respective central processing units while the main memory is shared by all the central processing units. To run such a multi-processor type data processing system under the control of the same program, it is necessary for every central processing unit to be able to use data belonging to another as well as common data stored in the main memory. Each central processing unit makes access to the main memory, independently of the others. Accordingly, if a central processing unit performs the writing of data into the main memory to replace a portion of the old data by new data, the other central processing units cannot use the correct, renewed data when their buffer memories store therein the data equal to the replaced portion of the old data. This problem can be solved by the means described in detail in, for example, U.S. Pat. No. 3,618,040; Japanese Patent Publication No. 12020/74; and Japanese Patent Publication No. 1611/78. According to these prior art systems, the central processing unit which has written data onto the main memory, sends the address of the written data to all the other central processing units. Each of the other central processing units checks whether its buffer memory stores data having the received address. If the buffer stores the data having the address in question, the data is invalidated to prevent a misuse of data.
In these prior art systems, therefore, each central processing unit is provided with interface circuits for the respective central processing units to effect address transfer in case of rewriting occurring in the main memory. If this system uses four central processing units, the number of the interface circuits to be used is determined depending on the four units. Therefore, when this system is run with only two of the central processing units in operation, the interface circuits for the two units at rest are superfluous.
If a data processing system is optimized (or standardized) using interface circuits corresponding to the greatest number of central processing units to be used in the case where the system is to be operated as a single processor type system or a multi-processor type system, then some of the interface circuits become superfluous in some cases. This is not preferable in view of cost performance. In the case of a general-purpose computer having a large capacity, for example, it is operated most often as a two multi-processor or a single processor type data processing system. It is therefore useful to design a data processing system in such a manner that it can also operate as a three or four processor system while it is optimized as a single or two processor system.